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ESDALC6V1P6
QUAD LOW CAPACITANCE TRANSILTM ARRAY FOR ESD PROTECTION
ASD
MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : Computers Printers Communication systems and cellular phones Video equipment This device is particularly adapted to the protection of symmetrical signals.

FEATURES 4 Unidirectional TransilTM functions Breakdown voltage VBR = 6.1 V min. Low diode capacitance (12pF @ 0V) Low leakage current < 500 nA

SOT-666IP (Internal Pad) FUNCTIONAL DIAGRAM
Very small PCB area < 2.6 mm2 Lead-free package
I/O1
DESCRIPTION The ESDALC6V1P6 is a monolithic array designed to protect up to 4 lines against ESD transients. The device is ideal for situations where board space saving is required. BENEFITS High ESD protection level High integration Suitable for high density boards COMPLIES WITH THE FOLLOWING STANDARDS:
I/O4 GND I/O3
GND I/O2
IEC61000-4-2 level 4: 15kV (air discharge) 8kV (contact discharge) MIL STD 883E-Method 3015-7: class3
Order Codes Part Number ESDALC6V1P6
Marking D
November 2005
REV. 4
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ABSOLUTE RATING (Tamb = 25C) Symbol VPP PPP Tj Tstg TL Top ESD discharge Parameter IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Tj initial = Tamb Value 15 8 30 125 -55 to +150 260 -40 to +125 Unit kV W C C C C
Peak pulse power (8/20s) (see note 1) Junction temperature Storage temperature range
Maximum lead temperature for soldering during 10 s at 5mm for case Operating temperature range
Note 1: for a surge greater than the maximum values, the diode will fail in short-circuit.
THERMAL RESISTANCES Symbol Rth(j-a) Parameter Junction to ambient on printed circuit on recommended pad layout Value 220 Unit C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VRM VBR VCL IRM IPP T VF C Rd Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Forward voltage drop Capacitance Dynamic resistance
Slope: 1/Rd IPP VF VCL VBR VRM IRM V IF I
VBR Part Number min. V ESDALC6V1P6 6.1 max. V 7.2
@ IR
IRM max.
@
VRM
Rd typ.
T max. 10 /C 4.5
-4
C typ. @ 0V pF 12
mA 1
A 0.5
V 3
1.5
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Fig. 1: Peak power dissipation versus initial junction temperature.
PPP[Tj initial] / PPP[Tj initial=25C]
1.1 1.0 0.9 0.8 0.7 0.6
Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25C).
PPP(W)
1000
Tj initial = 25C
100
0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150
Tj initial (C)
10 1
tp(s)
10 100
Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25C). Rectangular waveform tp = 2.5s.
IPP(A)
100.0
tp = 2.5s
Fig. 4: Peak forward voltage drop versus peak forward current (typical values).
IFM(A)
1.E+00
Tj = 125C Tj = 25C
10.0
1.E-01
1.0
1.E-02
0.1 0 10 20
VCL(V)
1.E-03
30 40 50 60 70
VFM(V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Fig. 5: Capacitance versus reverse applied voltage (typical values).
C(pF)
13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6
F=1MHz VOSC=30mVRMS Tj=25C
Fig. 6: Relative variation of leakage current versus junction temperature (typical values).
IR[Tj] / IR[Tj=25C]
1000
VR = 3V
100
10
VR(V)
1 25 50
Tj(C)
75 100 125
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TECHNICAL INFORMATION 1. ESD protection by ESDALC6V1P6 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems. As a transient voltage suppressor, ESDALC6V1P6 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDALC6V1P6. Fig. A: Application example.
I/O2
Connector
I/O1 I/O4 I/O3
IC to be protected
ESDALC6V1P6 serves as a parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the ESDALC6V1P6 becomes a low impedance path diverting the transient current to ground. The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor. Fig. A2: ESD clamping behavior.
RG IPP Rd VG VBR
ESD surge ESDALC6V1P6 Device to be protected
V(i/o)
RLOAD
I
slope =
1 Rd
VCL = VBR +Rd x IPP
IPP
V
VBR VCL
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis:
R G > R d ""and""R load > R d
we have:
VG V ( i o ) = V BR + R d x ------RG
The results of the calculation done VG = 8kV, RG = 330 (IEC61000-4-2 standard), VBR = 6.4V (typ.) and Rd = 1.5 (typ.) give:
V ( i o ) = 42.8 Volts
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side.
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Fig. A3: ESD test board. Fig. A4: ESD test condition.
15kV ESD Air discharge
I/O1, I/O2, I/O3 or I/O4 15kV ESD Air discharge
V(i/o)
V(i/o)
GND
ESDALC6V1P6
The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to VBR (positive way, figure A5a) and -VF (negative way, figure A5b). Fig. A5: Remaining voltage during ESD surge.
a: Response in the positive way
b: Response in the negative way
One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b.
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2. Crosstalk behavior Fig. A6: Crosstalk phenomenon.
RG1
Line 1
VG1
RL1
RG2
1VG1 + 12VG2
Line 2
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( 12 or 21 ) increase when the gap across lines decreases, particularly in silicon dice. In the example above, the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG2. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k). Fig. A7: Analog crosstalk test configuration.
50 I/O1 unloaded
Fig. A8: Typical analog crosstalk response.
0.00 dB -10.00
-20.00
VG
Port 1 GND
-30.00
-40.00
-50.00
-60.00
50 I/O4 Port 2
-70.00
-80.00
-90.00
-100.00 100.0k 1.0M 10.0M f/Hz 100.0M 1.0G
Figure A7 gives the measurement circuit for the analog crosstalk application. In figure 8, the curve shows the effect of the cell I/O1 on the cell I/O4. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -55dB.
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Fig. A9: Digital crosstalk test configuration.
I/O1
Fig. A10: Typical digital crosstalk response.
unloaded
VG1
VG1 0 - 5V pulse generator F= 100kHz tR = 20ns GND 21VG1 unloaded I/O4
21VG1
Figure A9 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A10 shows that in such a condition, ie signal from 0 to 5V and rise time of a few ns, the impact on the disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges give an impact within the same range. 3. PCB layout recommendations As ESD is a fast event, the dI/dt caused by this surge is about 30A/ns (risetime=1ns, Ipeak=30A), that means each nH causes an overvoltage of 30V. Thus, the circuit board layout is a critical design step in the suppression of ESD induced transients by reducing parasitic inductances. To ensure that, the following guidelines are recommended :

The ESDALC6V1P6 should be placed as close as possible to the input terminals or connectors. The path length between the ESD suppressor and the protected line should be minimized. All conductive loops, including power and ground loops should be minimized. The ESD transient return path to ground should be kept as short as possible. The connections from the ground pins to the ground plane should be the shortest possible.
4. Comparison with varistors Varistors Leakage current Protection efficiency Ageing Low leakage current for TransilTM device
Improve the autonomy of portable equipments as mobile Better efficiency in terms of ESD protection by using TransilTM device
TRANSILTM +++ ++ ++
----
Varistors are bidirectional devices and so are not suitable to protect sensitive ICs, because they will be submitted to high voltages in the negative way. Ratio VCL/VBR lower for TransilTM device
Less dispersion in terms of VBR No ageing phenomena regarding ESD events with TransilTM device
Higher efficiency in terms of ESD protection
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PACKAGE MECHANICAL DATA SOT-666IP (internal Pad)
b L3 e
DIMENSIONS REF. A Millimeters Min. 0.53 0.13 1.50 1.05 1.50 1.10 0.23 0.11 0.10 0.05 0.83 Ref 0.14 0.20 8 12 0.25 0.34 8 A3 D D2 E E1 E2 L1
A3
Inches Min. 0.021 0.005 0.059 0.041 0.059 0.043 0.009 0.004 0.004 0.002 0.032 0.006 0.010 0.013 0.020 0.008 12 Max. 0.024 0.007 0.067 0.049 0.067 0.051 0.017 0.010 0.012 -
Max. 0.60 0.18 1.70 1.25 1.70 1.30 0.43 0.26 0.30 -
L1
L4
b1
e1
(4x)
A
L2 L3 L4 b b1
D
E
E1
e e1
0.50 Bsc
L2
FOOT PRINT DIMENSIONS (in millimeters)
0.50
0.30
0.99 0.21 0.62 1.40 2.60
0.20
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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ORDER CODE
ESDA LC 6V1 P6
ESD ARRAY VBR min LOW CAPACITANCE PACKAGE: SOT-666IP
ORDERING INFORMATION Part Number ESDALC6V1P6 Marking D Package SOT-666IP Weight 2.9 mg Base qty 3000 Delivery mode Tape & reel
REVISION HISTORY Table 1: Revision history Date January-2004 25-May-2004 05-Jul-2004 02-Nov-2005 Revision 1 2 3 4 First issue SOT-666 Internal Pad version package change Stylesheet update. No content change. Lead-free statement added. Footprint diagram modified. Ordering information and revision history moved to end of datasheet. Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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